Most integrated circuits include many synchronized components. These synchronized components can include logic gates, inverters, flip-flops, memory cells and the like. Synchronized components are triggered by a clock signal. The clock signals are distributed among the synchronized components using clock distribution networks (also referred to as clock trees).
A typical clock tree includes multiple clock tree branches and multiple clock tree taps. Each clock tree branch splits to multiple clock tree taps. Clock signals propagate along a common clock path and then propagate along non-common clock paths. The non-common clock paths can include passive and optionally active components that can have different characteristics. These components can introduce clock skews. Clock skews can cause timing violations such as setup violations and/or hold violations.
There are multiple prior art methods and systems for reducing clock skews and for measuring clock skews. Some clock skew reduction methods are implemented during the design stages of the integrated circuit while other techniques can be implemented after production. A first method involved optimizing the topology of the clock tree. This method can include designing balanced clock trees and the like. Another clock skew reduction method involves clock reversing. Yet another clock skew reduction method included introducing delays in a large number of clock tree branches. The following articles, patents and patent applications illustrate various clock skew reduction methods and systems: “Reduced delay uncertainty in high performance clock distribution networks”, D. Velenis, M. C. Papaefthymiou, E. G. Friedman, Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE '03) 1530-1591/03; “Clock generation and distribution for the 130-nm Itanium® processor with 6-MB on-die L3 cache”, S. Tam, R. D. Limaye, U. N. Desai, IEEE journal on solid-state circuits, vol. 39, no. 4, April 2004; U.S. patent application publication Ser. No. 2004/0128634 of Johnson et al.; U.S. patent application publication Ser. No. 2005/0107970 of Franch et al.; U.S. patent application publication Ser. No. 2005/0102643 of Hou, et al.; U.S. patent application publication Ser. No. 2003/0101423 of Thorp, et al.; U.S. patent application publication Ser. No. 2004/0181705 of Gauthier, et al.; U.S. patent application publication Ser. No. 2002/0196067 of Schultz; U.S. Pat. No. 6,957,357 of Liu; U.S. Pat. No. 6,943,610 of Saint-Laurent; U.S. Pat. No. 6,941,532 of Haritsa et al. and U.S. Pat. No. 6,741,122 of Kapoo.
There is a need to provide efficient systems and methods for reducing clock skew.